Dr. Sayoon Kang, Vice President
Samsung Electro-Mechanics, Korea
|Title: “Wafer Level 3D Application for Tera-byte Node”
Prof. Takayuki Ohba, Ph.D.
Tokyo Institute of Technology (Tokyo Tech), Japan
The prospect of three-dimensional (3D) integration for Terabyte large scale integration using bumpless interconnects with low-aspect-ratio TSVs and ultra-thinning are discussed. Bumpless (no bump) interconnects between wafers are a second-generation alternative to the use of micro-bumps for Wafer-on-Wafer (WOW) technology. Ultra-thinning of wafers down to 4μm provides the advantage of a small form factor, not only in terms of the total volume of 3D ICs, but also the aspect ratio of Through-Silicon-Vias (TSVs). The bumpless interconnects technology can increase the number of TSVs per chip with a finer pitch of TSVs and lower the impedance of the TSV interconnects with no bumps. Therefore, a promising operating platform with a higher speed by enhancing parallelism, lower power by no bumps, and smaller size by thinning wafers can realize.
- 1984-2003 Fujitsu Limited
- 1994-1995 Tohoku University, Ph.D.
- 2004-2013 The University of Tokyo, Professor
- 2013- Tokyo Institute of Technology, Professor
- Filed: Advanced FEOL/BEOL process integration, 300-mm wafer level 3D process integration, high-dense with lowest impedance TSV interconnects, and Thermal Engineering