|Title: The Future of Electronic Packaging Industry
Dr. Sayoon Kang, Vice President
Samsung Electro-Mechanics, Korea
Over the past decade, 4G cellular phones have driven the IT technology.
4G cell phone, represented by “Mobility”, had a significant impact on the semiconductor industry.
For example, “how do we implement low power character improvements?”
In order to satisfy the low power consumption requirement, many semiconductor companies have improved IC design and fabrication scale-down methods that will continue to use mainly in the future.
In the coming future a dramatic technological changes are expected that we could not imagined before.
These changes will occur in various IT products and applications. Among them, 5G communication and AI will be the core technologies.
The 5G of the Multi/Fast Interconnection feature and AI of the Data Generation/Application characteristic will cause huge changes in the semiconductor industry, that is, opportunity and crisis.
Explosive demand of silicon chips is an opportunity factor.
On the other hand, the fabrication scaling-down can be a crisis due to it’s cost increase from huge investments, however, it can be an opportunity for the electronic package industry.
In this presentation, I want to show “What and how shoud package industry prepare for the coming big opportunities of 5G and AI era?”.
Dr. Sayoon Kang who is working at the SEMCO has been developing new packaging technology using a substrate.
Before joining Semco, he has developed several advanced packaging technologies at Samsung Electronics for 25 years.
|Title: “Wafer Level 3D Application for Tera-byte Node”
Prof. Takayuki Ohba, Ph.D.
Tokyo Institute of Technology (Tokyo Tech), Japan
The prospect of three-dimensional (3D) integration for Terabyte large scale integration using bumpless interconnects with low-aspect-ratio TSVs and ultra-thinning are discussed. Bumpless (no bump) interconnects between wafers are a second-generation alternative to the use of micro-bumps for Wafer-on-Wafer (WOW) technology. Ultra-thinning of wafers down to 4μm provides the advantage of a small form factor, not only in terms of the total volume of 3D ICs, but also the aspect ratio of Through-Silicon-Vias (TSVs). The bumpless interconnects technology can increase the number of TSVs per chip with a finer pitch of TSVs and lower the impedance of the TSV interconnects with no bumps. Therefore, a promising operating platform with a higher speed by enhancing parallelism, lower power by no bumps, and smaller size by thinning wafers can realize.
- 1984-2003 Fujitsu Limited
- 1994-1995 Tohoku University, Ph.D.
- 2004-2013 The University of Tokyo, Professor
- 2013- Tokyo Institute of Technology, Professor
- Filed: Advanced FEOL/BEOL process integration, 300-mm wafer level 3D process integration, high-dense with lowest impedance TSV interconnects, and Thermal Engineering