Keynote Speakers

Title: “Advanced Packaging Technologies and Reliability Challenges for Exa-era Applications”
 
Dr. Kang-Wook Lee
VP, Package Development
SK Hynix, Korea

Abstract
With diminishing returns from traditional transistor scaling further improvements in power and performance of systems are likely to come from advanced packaging technologies.
Furthermore, the increased focus on mobile computing, IoT, HPC, cloud networking, autonomous driving, and AI has highlighted the need for improved form-factor, improved performance, and low power technologies. This can be achieved only via increased emphasis on advanced packaging concepts such as 2.5D/3D integration and fan-out packaging technologies.
2.5/3D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked system.
Fan-out packaging has more flexibility to integrate various functional components into hetero-integrated system in wafer level with lower cost.
However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies.
Further trend of 3D integration towards thinner chip, more layer stacking, and more joining density to maximize area efficiency and performance. 2.5D and fan‐out packaging requires finer width/space, multi-layers of Cu RDL and large package size for multi-dies integration.
These trends could induce severe reliability challenges.
This session will address advanced packaging revolution and reliability challenges of 2.5D/3D and fan-out packaging for exa-era systems.

Biography
Kang-Wook Lee is currently VP, Package Development, SK Hynix, Korea.
He received the Ph.D. degree in machine intelligence and systems engineering from Tohoku University, Japan, in 2000. From 2000 to 2001, he was a Researcher with Japan Science and Technology Corporation, Japan. From 2001 to 2002, he was a Postdoctoral Researcher with the Department of Electrical, Computer, and Systems Engineering, Rensselaer Polytechnic Institute, Troy, NY, USA.
From 2002 to 2008, he worked with Memory Division, Samsung Electronics Ltd., Korea, as a Principal Engineer. From 2008 to 2016, he worked with the New Industry Creation Hatchery Center (NICHe), Tohoku University, Japan as a Professor.
From 2017 to 2018, he worked with R&D, Amkor Technology Korea, as a VP.
He has led the development of 2.5D/3D integration technologies for high performance/density memories, multi-functional convergence systems, wafer-level fan-out packaging for system scale, and the reliability studies about the impacts of 3D integration process on device performance.
Dr. Lee has authored more than 230 scientific publications, co-edited 4 books, and given couples of tutorial/short course/invited/keynote talks in international conferences at IEEE IEDM, IEEE IRPS, and IEEE EDAPS.
He has served as a frequent reviews for journals, including IEEE EDL, IEEE T-ED, IEEE CPMT, and technical program committees of international conferences, including IEEE IRPS, IEEE ECTC, IEEE EDTM, IEEE 3DIC.
He is a Senior Member of IEEE.


Title: “From Monolithic to Polylithic Integrated Circuits: A New Age for Moore’s Law”
 
Prof. Muhannad S. Bakir
School of Electrical and Computer Engineering
Georgia Tech, USA

Abstract
Monolithic ICs have progressed at an unprecedented rate of innovation in the past ~60 years. But, with Moore’s Law slowing down, ‘polylithic’ integration of heterogeneous ICs (or chiplets) is projected to be a key driver for the next era of Moore’s Law. This presentation will discuss polylithic integration ap-proaches using 2.5D and 3D IC technologies and their advantages. Specifically, we first discuss various 2.5D approaches including Heterogeneous Interconnect Stitching Technology (HIST), which enables the interconnection of multiple dice of various functionalities (including photonics) in a manner that mimics monolithic-like performance, yet utilizes advanced off-chip interconnects and packaging to provide flexi-bility in IC fabrication and design, improved scalability, reduced development time, and reduced cost. A key feature of HIST is the ability to place a ‘stitch chip’ between adjacent ICs on the surface of an or-ganic/ceramic package and use multi-height I/Os to interface the active dice to the package and stitch-chips simultaneously. Design considerations and benchmarking of power delivery, signaling, and thermal are described. Moreover, we show how such design considerations drive technology development in 2.5D/3D ICs along with experimental demonstrations. Secondly, we demonstrate embedded microfluidic cooling in 3D ICs along with TSV integration approaches to enable dense 3D electronics with no thermal limits; a Stratix-V FPGA with monolithic microfluidic cooling along with its performance benefits will also be shown. TSVs with deep sub-micron diameters are also shown for fine-grain 3D polylithic integration. Third, and lastly, we discuss 3D interconnect technologies for applications in CMOS multimodal biosen-sors.

Biography
Muhannad S. Bakir is a Professor in the School of Electrical and Computer Engineering at Georgia Tech. Dr. Bakir and his research group have received thirty conference and student paper awards including six from the IEEE Electronic Components and Technology Conference (ECTC), four from the IEEE Interna-tional Interconnect Technology Conference (IITC), and one from the IEEE Custom Integrated Circuits Conference (CICC). Dr. Bakir’s group was awarded 2014 and 2017 Best Papers of the IEEE Transactions on Components Packaging and Manufacturing Technology (TCPMT). Dr. Bakir is the recipient of the 2013 Intel Early Career Faculty Honor Award, 2012 DARPA Young Faculty Award, 2011 IEEE CPMT Society Outstanding Young Engineer Award, and was an Invited Participant in the 2012 National Academy of En-gineering Frontiers of Engineering Symposium. Dr. Bakir is the recipient of the 2018 IEEE Electronics Packaging Society (EPS) Exceptional Technical Achievement Award “for contributions to 2.5D and 3D IC heterogeneous integration, with focus on interconnect technologies.” He is also the co-recipient of the 2018 McKnight Foundation Technological Innovations in Neuroscience Awards.

Dr. Bakir serves on the editorial board of IEEE Transactions on Components, Packaging and Manufactur-ing Technology (TCPMT) and IEEE Transactions on Electron Devices (TED). Dr. Bakir serves as a Distin-guished Lecturer for IEEE EPS.


Title: “Could the reliability of solder joints be assessed accurately by using the Weibull distribution?”
 
Prof. Sung Yi
Mechanical and Materials Engineering Department
Portland State University, USA

Abstract
Solder Joint Reliability (SJR) is the probability that solder joints will provide proper electrical and mechanical connections over a specific period of time (design life) under the design operating condi-tions without failures. Reliability and lifetime predictions of solder joints in electronic packages have been one of the most difficult problems in the electronics industry. In general, in order to evaluate the reliability of solder joints, accelerated temperature cycle tests are conducted. The experimental determi-nation of the fatigue life of the solder joints in electronic packages is a very time consuming process. After conducting accelerated temperature cycle tests, the failure data are further analyzed by the Weibull analysis to determine the Weibull parameters and the mean life. However, many previous studies show that the Weibull analysis may significantly underestimate or overestimate the reliability and the mean life to failure. The underestimation of the times to solder joint failures may result in fatal failures. For exam-ple, on 28 December 2014, Indonesia Air Asia Flight 8501, an Airbus A320-216, crashed into the Java Sea during bad weather, killing all 155 passengers and seven crew on board. On 1 December 1 2015, Indo-nesia’s National Transportation Safety Committee stated that the cracking of a solder joint of both chan-nel A and B resulted in loss of electrical continuity and two flight augmentation computer (FAC) fault, which caused the autopilot and auto-thrust disengaged and contributed to the subsequent loss of con-trol and a malfunction in two of the plane’s rudder travel limiter units. On the other hand, the overesti-mation of the times to failure may lead to consequently underestimating the maintenance interval, which may unnecessarily increase the maintenance cost.
The goal of this study is to propose a general machine learning framework to predict the relia-bility of solder joints accurately for electronic devices and systems. In this study, it will be demonstrated how to achieve this goal using the machine learning method.

Biography
Currently Sung Yi is a Professor and Chair of Mechanical and Material Engineering Department at the Portland State University, OR. He received Ph.D. from University of Illinois at Urbana-Champaign in 1992. Previously, he was a faculty member and Head of Engineering Mechanics Division, School of Mechanical Engineering, Nanyang Technological University, Singapore. He was also a Singapore-MIT Alliance Fellow from 1998 to 2002. From 2006 to 2009, he served as a Vice President at R&D Institute, Samsung Electro-Mechanics. In Samsung, he was privileged to build a brand new microelectronic packaging team. He and
his team developed several advanced electronic and MEMS packaging technologies including embed-ding active devices and passives into organic substrates, the world’s smallest SAW filter using wafer level packaging, ALOX high thermal dissipation substrate technology for power devices and LED devices, 3-D advanced packaging technology, etc. He has published more than 220 papers in various journals and conference proceedings. He is an editorial advisory board member for the Journals of Soldering and Sur-face Mount Technology since 1998. He also served as an associate editor for ASME: Journal of Electronic Packaging from 2001 to 2004. He received the Jefferson Goblet Paper Award at the 32nd SDM Confer-ence in 1991 and the Roger A. Strehlow Memorial Award from UIUC in 1992, respectively. He also re-ceived Intel Learning Star Award in 2009 and Hedong Technology Award in 2007, respectively.


Title: “Electroplated Cu Bump with Ultra-Large Grain without Thermal Annealing and Kirkendall Void at the Interface of Cu/Sn Joint”
 
Prof. Wei-Ping Dow
Tenured Distinguished Professor Department of Chemical Engineering
National Chung Hsing University, Taiwan

Abstract
Sn-containing solder is still comprehensively used for chip packaging. Not only copper pillar but also copper bump will contact the Sn-containing solder. However, after the soldering process, not only IMC but also Kirkendall voids will be formed, which leads to poor reliability. In this work, copper bump was formed by electroplating at 25 ~ 35℃. After the copper electroplating, the copper bump has a grain size of 15 ~ 20 μm. Moreover, it has a preferred orientation of (111). Since the grain size is so big, it does not need to be annealed after electroplating. Also, it has no Kirkendall voids after soldering process at 200℃ for 1000 hr.

Biography

  1. Educational background: Ph.D. of Chemical Engineering, National Tsing Hua University (1995), Tai-wan.
  2. Active position: Tenured Distinguished Professor, National Chung Hsing University, Taiwan.
  3. Professional specialty: Electroplating, Electroless deposition, Formulation and process Development for electronic devices and products fabrication
  4. Experience:
    – DRAM process engineer, Vanguard International Semiconductor Corporation, Taiwan.
    – Technology service engineer, Electrochemical Inc., USA.
    – D&R supervisor, Electrochemical Inc., USA.
    – Assistant Processor, National Yun-Lin University of Science & Technology, Taiwan.
    – Associate Professor, National Yun-Lin University of Science & Technology, Taiwan.
    – Associate Professor, National Chung Hsing University, Taiwan.
    – Professor, National Chung Hsing University, Taiwan.
    – Distinguished Professor (III), National Chung Hsing University, Taiwan.
    – Distinguished Professor (II), National Chung Hsing University, Taiwan.
  5. Academic activities:
    – Electrochemical Society (ECS): Active Member, Invited Speaker, Meeting Organizer
    – International Electrochemistry Society (ISE): Active Member, Meeting Organizer
    – Electrochimca Acta, Guest Editor of Special Issue
    – Journal of the Taiwan Institute of Chemical Engineers, Deputy Editor.
    Publication and Patent: 73 articles; 26 patents
  6. Honor
    – National Industrial Innovation Award, Ministry of Economic Affairs, Taiwan, 2019.
    – Breakthrough Award of Future Technology, Ministry of Science and Technology, Taiwan, 2018.
    – Outstanding Performance Award of Technology Alliance Project, Ministry of Science and Technology, Taiwan, 2018.
    – Outstanding Award of Technology Transfer, National Chung Hsing University, Taiwan, 2017.
    – Outstanding Research Award, Ministry of Science and Technology, Taiwan, 2015.
    – Excellent Research Award, National Chung Hsing University, Taiwan, 2011 and 2014.
    – Outstanding Industry Collaboration Award, Engineering College, National Chung Hsing University, Taiwan, 2012, 2015 and 2018.
    – Excellent Industry Collaboration Award, Engineering College, National Chung Hsing University, Tai-wan, 2011, 2013 and 2014.
    – Outstanding Research Award of LCY Chemical Education Foundation, Taiwan, 2011.
    – Invited by international conferences as speaker: 14, where one was invited by Golden Research Conference, 2010, USA.
    – Conference award: 24, where 4 are golden award, 1 is silver award.